One of the main features Intel was promoting at the launch of Haswell was TSX – Transactional Synchronization eXtensions. In our analysis, Johan explains that TSX enables the CPU to process a series of traditionally locked instructions on a dataset in a multithreaded environment without locks, allowing each core to potentially violate each other’s shared data. If the series of instructions is computed without this violation, the code passes through at a quicker rate – if an invalid overwrite happens, the code is aborted and takes the locked route instead. All a developer has to do is link in a TSX library and mark the start and end parts of the code.
News coming from Intel’s briefings in Portland last week boil down to an erratum found with the TSX instructions. Tech Report and David Kanter of Real World Technologies are stating that a software developer outside of Intel discovered the erratum through testing, and subsequently Intel has confirmed its existence. While errata are not new (Intel’s E3-1200 v3 Xeon CPUs already have 140 of them), what is interesting is Intel’s response: to push through new microcode to disable TSX entirely. Normally a microcode update would suggest a workaround, but it would seem that this a fundamental silicon issue that cannot be designed around, or intercepted at an OS or firmware/BIOS level.
Holy sh*t, ovo je prilicno gadan f*ckup.
TSX ekstenzije su hype-ovane izuzetno za ubrzanje multithreaded koda, pogotovu enormnih baza podataka.
Nezavisni tester je otkrio bug u instrukcijama i, kako stvari stoje, Intel nije imao drugu mogucnost popravke u microcode-u vec su morali da izbace MC update koji iskljucuje TSX!!!
Tajming je gadan, posto su Haswell EP procesori vec u masovnoj produkciji, i vrlo verovatno je gomila vec zavrsila kod jakih kupaca...
Ovo ce da kosta...
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